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Dual 256-Position SPI Digital Potentiometer AD5162
FEATURES
2-channel, 256-position End-to-end resistance: 2.5 k, 10 k, 50 k, 100 k Compact MSOP-10 (3 mm x 4.9 mm) package Fast settling time: tS = 5 s typical on power-up Full read/write of wiper register Power-on preset to midscale Extra package address decode pin AD0 Computer software replaces C in factory programming applications Single supply: 2.7 V to 5.5 V Low temperature coefficient: 35 ppm/C Low power: IDD = 6 A max Wide operating temperature: -40C to +125C Evaluation board available
FUNCTIONAL BLOCK DIAGRAM
A1 W1 B1 W2 B2
VDD WIPER REGISTER 1 GND A= 0 CLK SPI INTERFACE
04108-0-001
WIPER REGISTER 2 A=1
AD5162
SDI CS
Figure 1.
APPLICATIONS
Systems calibrations Electronics level settings Mechanical Trimmers(R) replacement in new designs Permanent factory PCB setting Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5162 provides a compact 3 mm x 4.9 mm packaged solution for dual 256-position adjustment applications. This device performs the same electronic adjustment function as a 3-terminal mechanical potentiometer. Available in four different end-to-end resistance values (2.5 k, 10 k, 50 k, 100 k), this low temperature coefficient device is ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through an SPI digital interface. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC1 latch. Operating from a 2.7 V to 5.5 V power supply and consuming less than 6 A allows the AD5162 to be used in portable battery-operated applications. For applications that program the AD5162 at the factory, Analog Devices offers device programming software running on Windows(R) NT/2000/XP operating systems. This software effectively replaces any external SPI controllers, which in turn enhances users' systems time-to-market. An AD5162 evaluation kit and software are available. The kit includes a cable and instruction manual.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5162 TABLE OF CONTENTS
Electrical Characteristics--2.5 k Version ................................... 3 Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4 Timing Characteristics--All Versions ........................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Pin Configuration......................................................................... 7 Pin Function Descriptions .......................................................... 7 Typical Performance Characteristics ............................................. 8 Test Circuits..................................................................................... 12 Theory of Operation ...................................................................... 13 Programming the Variable Resistor and Voltage.................... 13 Programming the Potentiometer Divider............................... 14 ESD Protection ........................................................................... 14 Terminal Voltage Operating Range.......................................... 14 Power-Up Sequence ................................................................... 14 Layout and Power Supply Bypassing ....................................... 15 Constant Bias to Retain Resistance Setting............................. 15 Evaluation Board ........................................................................ 15 SPI Interface .................................................................................... 16 SPI Compatible 3-Wire Serial Bus ........................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
11/03 Changed from REV. 0 to REV. A: Changes to Electrical Characteristics.................................... Page 3 11/03 Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5162 ELECTRICAL CHARACTERISTICS--2.5 k VERSION
Table 1. VDD = 5 V 10%, or 3 V 10%; VA = +VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted
Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 TA = 25C RAB Resistance Temperature Coefficient (RAB/RAB )/T VAB = VDD, wiper = no connect RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Differential Nonlinearity4 DNL Integral Nonlinearity INL (VW/VW)/T Code = 0x80 Voltage Divider Temperature Coefficient Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA, B, W Capacitance6 A, B CA, B f = 1 MHz, measured to GND, Code = 0x80 Capacitance6 W CW f = 1 MHz, measured to GND, Code = 0x80 Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance6 CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation7 PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = 5 V 10%, Code = midscale 8 DYNAMIC CHARACTERISTICS Bandwidth -3 dB BW_2.5 K Code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz VW Settling Time tS VA = 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 1.25 k, RS = 0
See notes at end of section.
Min -2 -6 -20
Typ1 0.1 0.75 35 160
Max +2 +6 +55 200 +1.5 +2
Unit LSB LSB % ppm/C LSB LSB ppm/C LSB LSB V pF pF nA V V V V A pF V A W %/% MHz % s nV/Hz
-1.5 -2
0.1 0.6 15 -2.5 2
-10 0 GND
0 10 VDD
45 60 1 2.4 0.8 2.1 0.6 1 5 2.7 3.5 0.02 4.8 0.1 1 3.2 5.5 6 30 0.08
Rev. A | Page 3 of 20
AD5162 ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
Table 2. VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; -40C < TA < 125C; unless otherwise noted
Parameter Symbol Conditions DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect Nominal Resistor Tolerance3 TA = 25C RAB Resistance Temperature Coefficient (RAB/RAB )/T VAB = VDD, wiper = no connect RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs) Differential Nonlinearity4 DNL 4 Integral Nonlinearity INL Voltage Divider Temperature Coefficient (VW/VW)/T Code = 0x80 Full-Scale Error VWFSE Code = 0xFF Zero-Scale Error VWZSE Code = 0x00 RESISTOR TERMINALS Voltage Range5 VA,B,W Capacitance6 A, B CA,B f = 1 MHz, measured to GND, Code = 0x80 6 Capacitance W CW f = 1 MHz, measured to GND, Code = 0x80 Common-Mode Leakage ICM VA = VB = VDD/2 DIGITAL INPUTS AND OUTPUTS Input Logic High VIH VDD = 5 V Input Logic Low VIL VDD = 5 V Input Logic High VIH VDD = 3 V Input Logic Low VIL VDD = 3 V Input Current IIL VIN = 0 V or 5 V Input Capacitance CIL POWER SUPPLIES Power Supply Range VDD RANGE Supply Current IDD VIH = 5 V or VIL = 0 V Power Dissipation PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V Power Supply Sensitivity PSS VDD = 5 V 10%, Code = midscale DYNAMIC CHARACTERISTICS Bandwidth -3 dB BW RAB = 10 k/50 k/100 k, Code = 0x80 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k VW Settling Time (10 k/50 k/100 k) tS VA = 5 V, VB = 0 V, 1 LSB error band Resistor Noise Voltage Density eN_WB RWB = 5 k, RS = 0
See notes at end of section.
Min -1 -2.5 -20
Typ1 0.1 0.25 35 160
Max +1 +2.5 +20 200 +1 +1 0 2.5 VDD
Unit LSB LSB % ppm/C LSB LSB ppm/C LSB LSB V pF pF nA V V V V A pF V A W %/%
-1 -1 -2.5 0 GND
0.1 0.3 15 -1 1
45 60 1 2.4 0.8 2.1 0.6 1 5 2.7 3.5 0.02 5.5 6 30 0.08
600/100/40 0.1 2 9
kHz % s nV/Hz
Rev. A | Page 4 of 20
AD5162 TIMING CHARACTERISTICS--ALL VERSIONS
Table 3. VDD = +5 V 10%, or +3 V 10%; VA = VDD; VB = 0 V; -40C < TA < +125C; unless otherwise noted
Parameter Symbol Conditions SPI INTERFACE TIMING CHARACTERISTICS9 (Specifications Apply to All Parts) Clock Frequency fCLK Input Clock Pulse Width tCH, tCL Clock level high or low Data Setup Time tDS Data Hold Time tDH tCSS CS Setup Time tCSW CS High Pulse Width tCSH0 CLK Fall to CS Fall Hold Time tCSH1 CLK Fall to CS Rise Hold Time tCS1 CS Rise to Clock Rise Setup
See notes at end of section.
Min
Typ1
Max 25
Unit MHz ns ns ns ns ns ns ns ns
20 5 5 15 40 0 0 10
NOTES
1 2
Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. 9 See timing diagrams for locations of measured values.
Rev. A | Page 5 of 20
AD5162 ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25C, unless otherwise noted
Parameter VDD to GND VA, VB, VW to GND Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1 Pulsed Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 s) Thermal Resistance2 JA: MSOP-10 Value -0.3 V to +7 V VDD
20 mA 5 mA 0 V to 7 V -40C to +125C 150C -65C to +150C 300C 230C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX - TA)/JA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 20
AD5162 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
B1 1 A1 2 W2 3 GND 4 VDD 5
10 9
PIN FUNCTION DESCRIPTIONS
Table 5.
W1 B2 CS
04108-0-002
AD5162
TOP VIEW
8 7 6
SDI CLK
Figure 2.
Pin No. 1 2 3 4 5 6 7 8
Mnemonic B1 A1 W2 GND VDD CLK SDI CS
9 10
B2 W1
Description B1 Terminal. A1 Terminal. W2 Terminal. Digital Ground. Positive Power Supply. Serial Clock Input. Positive edge triggered. Serial Data Input. Chip Select Input, Active Low. When CS returns high, data is loaded into the DAC register. B2 Terminal. W1 Terminal.
Rev. A | Page 7 of 20
AD5162 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 1.5
RHEOSTAT MODE INL (LSB)
0.5
TA = 25C RAB = 10k
POTENTIOMETER MODE DNL (LSB)
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
04108-0-003
RAB = 10k
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 32 64
VDD = 2.7V
VDD = 2.7V; TA = -40C, +25C, +85C, +125C
VDD = 5.5V
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 3. R-INL vs. Code vs. Supply Voltages
Figure 6. DNL vs. Code vs. Temperature
0.5 0.4 TA = 25C RAB = 10k
1.0 0.8 TA = 25C RAB = 10k
RHEOSTAT MODE DNL (LSB)
0.3 0.2 VDD = 2.7V 0.1 0 -0.1 -0.2 -0.3 -0.4
04108-0-004
POTENTIOMETER MODE INL (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 VDD = 2.7V VDD = 5.5V
VDD = 5.5V
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 4. R-DNL vs. Code vs. Supply Voltages
Figure 7. INL vs. Code vs. Supply Voltages
0.5 0.4 RAB = 10k
0.5 0.4 TA = 25C RAB = 10k
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
POTENTIOMETER MODE DNL (LSB)
POTENTIOMETER MODE INL (LSB)
VDD = 5.5V TA = -40C, +25C, +85C, +125C
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 VDD = 5.5V VDD = 2.7V
VDD = 2.7V TA = -40C, +25C, +85C, +125C
04108-0-005
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 5. INL vs. Code vs. Temperature
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. A | Page 8 of 20
04108-0-008
-0.5
-0.5
04108-0-007
-0.5
-1.0
04108-0-006
-0.5
AD5162
2.0 RAB = 10k 1.5 VDD = 2.7V TA = -40C, +25C, +85C, +125C 4.50 RAB = 10k
1.0 0.5 0 -0.5 -1.0 -1.5
04108-0-009
ZSE, ZERO-SCALE ERROR (LSB)
3.75
RHEOSTAT MODE INL (LSB)
3.00
2.25
VDD = 2.7V, VA = 2.7V
VDD = 5.5V TA = -40C, +25C, +85C, +125C
1.50 VDD = 5.5V, VA = 5.0V 0.75
0
32
64
96
128
160
192
224
256
-25
-10
5
20
35
50
65
80
95
110
125
CODE (DECIMAL)
TEMPERATURE (C)
Figure 9. R-INL vs. Code vs. Temperature
Figure 12. Zero-Scale Error vs. Temperature
0.5 0.4 RAB = 10k
10
RHEOSTAT MODE DNL (LSB)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 32 64 96 128 160 192 224 256
04108-0-010
VDD = 2.7V, 5.5V; TA = -40C, +25C, +85C, +125C
IDD, SUPPLY CURRENT (A)
VDD = 5V
1 VDD = 3V
-7
26
59
92
125
CODE (DECIMAL)
TEMPERATURE (C)
Figure 10. R-DNL vs. Code vs. Temperature
Figure 13. Supply Current vs. Temperature
2.0 RAB = 10k
120 RAB = 10k
1.0 0.5 0 -0.5 -1.0 -1.5
04108-0-011
RHEOSTAT MODE TEMPCO (ppm/C)
1.5
100
FSE, FULL-SCALE ERROR (LSB)
80 60 VDD = 2.7V TA = -40C TO +85C, -40C TO +125C VDD = 5.5V TA = -40C TO +85C, -40C TO +125C
VDD = 5.5V, VA = 5.0V
40
VDD = 2.7V, VA = 2.7V
20
0 -20 0 32 64 96 128 160 192 224 256 CODE (DECIMAL)
-25
-10
5
20
35
50
65
80
95
110
125
TEMPERATURE (C)
Figure 11. Full-Scale Error vs. Temperature
Figure 14. Rheostat Mode Tempco RWB/T vs. Code
Rev. A | Page 9 of 20
04108-0-014
-2.0 -40
04108-0-013
-0.5
0.1 -40
04108-0-012
-2.0
0 -40
AD5162
50
0
RAB = 10k
POTENTIOMETER MODE TEMPCO (ppm/C)
40 30 20 10 0 -10 -20
04108-0-015
-6 -12
0x80 0x40 0x20 0x10 0x08 0x04 0x02
VDD = 2.7V TA = -40C TO +85C, -40C TO +125C
-18
GAIN (dB)
-24 -30 -36 -42
VDD = 5.5V TA = -40C TO +85C, -40C TO +125C
0x01 -48 -54
0
32
64
96
128
160
192
224
256
1k
10k
100k FREQUENCY (Hz)
1M
CODE (DECIMAL)
Figure 15. Potentiometer Mode Tempco VWB/T vs. Code
Figure 18. Gain vs. Frequency vs. Code, RAB = 50 k
0 -6 -12 -18
GAIN (dB)
0 0x80 -6 0x40 -12 0x20 0x10
GAIN (dB)
0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01
-18 -24 -30 -36 -42 -48 -54
04108-0-016
-24 -30 -36 -42 -48 -54 -60 10k
0x08 0x04
0x02 0x01
100k FREQUENCY (Hz)
1M
10M
1k
10k
100k FREQUENCY (Hz)
1M
Figure 16. Gain vs. Frequency vs. Code, RAB = 2.5 k
Figure 19. Gain vs. Frequency vs. Code, RAB = 100 k
0 -6 -12 -18
GAIN (dB)
0 0x80 0x40 0x20 0x10
GAIN (dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54
04108-0-017
100k 60kHz 50k 120kHz 10k 570kHz 2.5k 2.2MHz
-24 -30
0x08 0x04 -36 -42 -48 -54 -60 1k 10k 100k FREQUENCY (Hz) 1M 0x02 0x01
1k
10k
100k FREQUENCY (Hz)
1M
10M
Figure 17. Gain vs. Frequency vs. Code, RAB = 10 k
Figure 20. -3 dB Bandwidth @ Code = 0x80
Rev. A | Page 10 of 20
04108-0-020
-60
04108-0-019
-60
04108-0-018
-30
-60
AD5162
10 TA = 25C
IDD, SUPPLY CURRENT (mA)
1 VDD = 5.5V
VW2
0.1 VDD = 2.7V
VW1
04108-0-024
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
Figure 21. IDD vs. Input Voltage
04108-0-025
0.01
Figure 24. Analog Crosstalk
VW
VW
CLK
04108-0-021 04108-0-026
Figure 22. Digital Feedthrough
Figure 25. Midscale Glitch, Code 0x80 to 0x7F
VW2
VW
VW1
04108-0-022
CS
Figure 23. Digital Crosstalk
Figure 26. Large Signal Settling Time
Rev. A | Page 11 of 20
04108-0-023
AD5162 TEST CIRCUITS
Figure 27 through Figure 32 illustrate the test circuits that define the test conditions used in the product specification tables.
DUT A V+ B W
04108-0-027
VA
V+ = VDD 10%
DUT
VDD A
V+ = VDD 1LSB = V+/2N
V+ B
W
VMS PSRR (dB) = 20 LOG VDD VMS% PSS (%/%) = VDD%
(
)
04108-0-030
VMS
VMS
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
DUT A W AD8610 VOUT
04108-0-031
04108-0-033
NO CONNECT DUT AW B VMS
04108-0-028
+15V
IW
OFFSET GND
VIN B
2.5V
-15V
Figure 31. Test Circuit for Gain vs. Frequency
Figure 28. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
NC DUT
DUT A VMS2 B VMS1 W VW
RW = [VMS1 - VMS2]/IW IW = VDD/RNOMINAL
VDD GND
04108-0-029
A B
ICM W VCM NC = NO CONNECT
NC
Figure 32. Test Circuit for Common-Mode Leakage Current
Figure 29. Test Circuit for Wiper Resistance
Rev. A | Page 12 of 20
AD5162 THEORY OF OPERATION
The AD5162 is a 256-position digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. The general equation determining the digitally programmed output resistance between W and B is
RWB (D ) = D x RAB + 2 x RW 256
(1)
PROGRAMMING THE VARIABLE RESISTOR AND VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B is available in 2.5 k, 10 k, 50 k, and 100 k. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings.
A W A W A W
04108-0-034
where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the ON resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is open circuited, the following output resistance RWB is set for the indicated RDAC latch codes. Table 6. Codes and Corresponding RWB Resistance
D (Dec) 255 128 1 0 RWB () 9,961 5,060 139 100 Output State Full scale (RAB - 1 LSB + RW) Midscale 1 LSB Zero scale (wiper contact resistance)
B
B
B
Figure 33. Rheostat Mode Configuration
Assuming that a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Because there is a 50 wiper contact resistance, such a connection yields a minimum of 100 (2 x 50 ) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 139 (RWB = RAB/256 + 2 x RW = 39 + 2 x 50 ) for data 0x01. The third connection is the next tap point, representing 178 (2 x 39 + 2 x 50 ) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (RAB + 2 x RW).
A RS
Note that, in the zero-scale condition, a finite wiper resistance of 100 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is
RWA (D ) = 256 - D x RAB + 2 x RW 256
(2)
D7 D6 D5 D4 D3 D2 D1 D0
RS
RS W
For RAB = 10 k and the B terminal open circuited, the following output resistance RWA is set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWA Resistance
D (Dec) 255 128 1 0 RWA () 139 5,060 9,961 10,060 Output State Full scale Midscale 1 LSB Zero scale
RDAC LATCH AND DECODER
RS B
04108-0-035
Figure 34. AD5162 Equivalent RDAC Circuit
Typical device-to-device matching is process lot dependent and may vary by up to 30%. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 35 ppm/C temperature coefficient.
Rev. A | Page 13 of 20
AD5162
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity.
VI A W VO
04108-0-036
ESD PROTECTION
All digital inputs are protected with a series of input resistors and parallel Zener ESD structures shown in Figure 36 and Figure 37. This applies to the digital input pins SDI, CLK, and CS.
340 LOGIC
04108-0-037
GND
Figure 36. ESD Protection of Digital Pins
B
A, B, W
04108-0-038
Figure 35. Potentiometer Mode Configuration
GND
If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to terminals A and B is
VW (D ) = 256 - D D VA + VB 256 256
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or GND are clamped by the internal forward biased diodes (see Figure 38).
VDD
(3)
A more accurate calculation, which includes the effect of wiper resistance, VW, is
R (D ) R (D ) VW (D ) = WB VA + WA VB RAB RAB
A W
(4)
B
04108-0-039
Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 15 ppm/C.
GND
Figure 38. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 38), it is important to power VDD/GND before applying any voltage to terminals A, B, and W; otherwise, the diode is forward biased such that VDD is powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VA, VB, VW. The relative order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND.
Rev. A | Page 14 of 20
AD5162
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 39). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
110% 108% 106%
BATTERY LIFE DEPLETED
TA = 25C
104% 102% 100% 98% 96% 94% 92% 90% 0 5 10 15 DAYS 20 25 30
04108-0-041
Figure 40. Battery Operating Life Depletion
VDD C3 10F
+
VDD C1 0.1F
EVALUATION BOARD
AD5162
GND
04108-0-040
An evaluation board, along with all necessary software, is available to program the AD5162 from any PC running Windows 98/2000/XP. The graphical user interface, as shown in Figure 41, is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board.
Figure 39. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5162 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5162 is designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. The graph in Figure 40 demonstrates the power consumption from a 3.4 V 450 mAhr Li-Ion cell phone battery, which is connected to the AD5162. The measurement over time shows that the device draws approximately 1.3 A and consumes negligible power. Over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. This demonstrates that constantly biasing the potentiometer is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5162 is lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5162. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly.
Figure 41. AD5162 Evaluation Board Software
The AD5162 starts at midscale upon power-up. To increment or decrement the resistance, the user may simply move the scrollbars on the left. To write any specific value, the user should use the bit pattern in the upper screen and press the Run button. The format of writing data to the device is shown in Table 8.
Rev. A | Page 15 of 20
AD5162 SPI INTERFACE
SPI COMPATIBLE 3-WIRE SERIAL BUS
The AD5162 contains a 3-wire SPI compatible digital interface (SDI, CS, and CLK). The 9-bit serial word must be loaded MSB first. The format of the word is shown in Table 8. The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 42). The data setup and data hold times in the specification table determine the valid timing requirements. The AD5162 uses a 9-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. Table 8. Serial Data-Word Format
B8 A0 MSB 28 B7 D7 27 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 LSB 20
1 SDI 0 1 CLK 0 1 CS 0 1 VOUT 0 RDAC REGISTER LOAD
04108-0-042
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 42. SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
SDI (DATA IN)
1 Dx 0 1 Dx
tCH
tDS
tCH
tCS1
CLK 0
tCSHO tCSS
1 CS 0
tCL
tCSH1
tCSW tS
VDD
VOUT 0
1LSB
Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
Rev. A | Page 16 of 20
04108-0-043
AD5162 OUTLINE DIMENSIONS
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 44. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5162BRM2.5 AD5162BRM2.5-RL7 AD5162BRM10 AD5162BRM10-RL7 AD5162BRM50 AD5162BRM50-RL7 AD5162BRM100 AD5162BRM100-RL7 AD5162EVAL
1
RAB () 2.5 k 2.5 k 10 k 10 k 50 k 50 k 100 k 100 k See Note 1
Temperature -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 MSOP-10 Evaluation Board
Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10
Branding D0Q D0Q D0R D0R D0S D0S D0T D0T
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. A | Page 17 of 20
AD5162 NOTES
Rev. A | Page 18 of 20
AD5162 NOTES
Rev. A | Page 19 of 20
AD5162 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04108-0-11/03(A)
Rev. A | Page 20 of 20

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